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Solicitation Number: TY-10-06
Agency: National Aeronautics and Space Administration
Office: Headquarters
Location: Office of Procurement (HQ)
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Sources Sought
Added: Nov 26, 2010 1:12 pm
The California Institute of Technology's Jet Propulsion Laboratory (Caltech/JPL),located in Pasadena, California, operating under a prime contract with NASA seeksinformation from potential contractors on the design, verification, manufacture, andvalidation of radiation hardened application specific integrated circuits (ASICs) insupport of the Jupiter Europa Orbiter mission (JEO).BACKGROUND: The Europa Jupiter System Mission (EJSM) is a joint NASA/European SpaceAgency (ESA) mission that would consist of two (2) flight elements exploring the Joviansystem: the NASA-led JEO, and the ESA-led Jupiter Ganymede Orbiter (JGO). JEO and JGOwould execute a choreographed exploration of the Jovian system before settling into orbitaround Europa and Ganymede, respectively. The launch of JEO would occur in 2020 witharrival at Jupiter in 2025. Jupiter Orbit Insertion (JOI) begins a 30-month Jovian systemtour followed by a 9-month science mapping phase after Europa Orbit Insertion (EOI) inJuly 2028. The orbiter will ultimately impact the surface of Europa after the mission iscompleted.The current JEO and JGO mission concepts include 11 and 10 complementary instruments,respectively, to monitor dynamic phenomena (such as Ios volcanoes and Jupitersatmosphere), map the Jovian magnetosphere and its interactions with the Galileansatellites, and characterize water oceans beneath the ice shells of Europa and Ganymede. Jupiter is approximately ten (10) times the size of the Earth while its magnetic momentis nearly twenty thousand (20,000) times stronger. As the magnetic field at the equatoris proportional to the magnetic moment divided by the cube of the radial distance, theJovian magnetic field is proportionally twenty (20) times larger than that of the Earth. The Jovian moons of interest lie well within the radiation belt. The resulting radiationenvironment for the current mission concept is estimated at 2.9 Mrad total ionizing dose(TID) behind 100 mil thick aluminum. This level is seven (7) times greater than anyprevious NASA mission.A pre-project office has been formed to begin preparation for this challenging mission.The pre-project is a joint undertaking of JPL and the Johns Hopkins University AppliedPhysics Laboratory (JHU/APL). JPL administers the release and response of this RFI.The JEO flight system is comparable in size and complexity to other spacecraft forsimilar missions such as Cassini or Mars Reconnaissance Orbiter (MRO). The concept wouldfeature full redundancy for engineering functions, 3-axis stabilized pointing,radioisotope power source (RPS) with batteries for peak power management, bi-propellantchemical propulsion, a large gimbaled high gain antenna (HGA), and X-band and Ka-bandtransponders for tracking, telemetry and precision Doppler measurements. The proposed ten(10) year mission would require that all electronic components be hardened to a minimumof 300 kRad, although lower tolerance level could be considered as exceptions in limitedcases where no alternative exists. The radiation challenges and long-duration demand thehighest reliability in spacecraft and instrument design capabilities.PURPOSE: JPL seeks to solicit candidate solutions for radiation hardened ASIC design,manufacturing, verification and validation from potential contractors. Mission assuranceand risk mitigation requirements of the JEO mission will require that any ASICs used onthe mission have been designed and verified with the most robust, thorough, and effectiveprocess possible in order to withstand the harsh radiation environment encountered duringthe mission lifetime. For digital designs, it is anticipated that prototypes in FieldProgrammable Gate Arrays (FPGA) will be designed and developed as intermediate productsfor use by the spacecraft and instrument design teams. Additional circuitries will berequired for mixed signal development. Potential ASIC providers to this RFI are requestedto address the translation of the FPGA design format, analog Intellectual Property (IP)cores, architecture, and radiation mitigation schemes to the candidate ASIC manufacturingprocess for both mixed signal and digital only designs. The specific design formatrequired for the manufacture of the ASICs are also requested in response to this RFI. REQUIREMENT: Respondents are requested to provide the following information: (1)processes, documentation, requirements, hardware and software tools, test benches, andany other relevant material as to why their proposed ASIC design, manufacturing, andverification and validation approach should be considered as a candidate solution for theJEO mission; (2) IP handling, foundry capability, radiation mitigation technology, andtesting capability; and (3) case studies, test chips if readily available, and/orpractical examples. Attached are information on the test chip and a list of questionsregarding the ASIC design, manufacturing, and verification and validation process thatare requested to be addressed (refer to Exhibit 1.) Additional questions can beexpected as the evaluation continues.The JEO Pre-project office (JPL and APL) will vet all submittals. The results of thisreview will be used to compile a list of recommended ASIC vendors for JEO (to be releasedas a public document on the EJSM web portal in the later half of calendar year 2011) andto develop guidelines for implementing ASICs on the JEO program. The results will bepublished as a JEO document for both spacecraft and instrument development teams.RESPONSE TO THE RFI: Please provide your response, including the following requiredinformation: (1) Company name and mailing address; (2) Contact person, phone, FAX number,and Email address; and (3) Company size (i.e., large business, small business, smalldisadvantaged business, woman-owned, Service-Disabled/Veteran owned, etc.) Please limityour written response to ten (10) pages.RESPONSE DEADLINE: Please submit the above-requested information to the attention of MaryHelen Ruiz at Email address: no later than Friday, January21, 2011.POINT OF CONTACT: Please direct any questions regarding this synopsis to Tsun-Yee Yan viaEmail at: yan@jpl.nasa.govDISCLAIMER: It is emphasized that the requested information is for preliminary planningpurposes only and does not constitute a commitment, implied or otherwise, that JPL willlet a solicitation in the future. Neither JPL nor the Government will be responsible forany costs incurred by you in furnishing this information. Be advised that any informationprovided shall be deemed to be furnished with unlimited rights to JPL and APL, with JPLand APL assuming no liability for the disclosure, use, or reproduction of such data.
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Exhibit 1. Test Chip & Ques. on ASIC Technologies

Other (Draft RFPs/RFIs, Responses to Questions, etc..)
Exhibit 1. Test Chip & Ques. on ASIC Technologies
Posted Date:
November 26, 2010
Description: Test Chip & Ques. on ASIC Technologies
NASA Management Office, Jet Propulsion Laboratory, 4800 Oak Grove Drive,Pasadena, CA 91109
Mary Helen Ruiz, JPL Business Opportunities Office, Phone 818-354-7532, Fax 818-393-1746, Email

Mary Helen Ruiz