Accessibility Information

Users of assistive technologies such as screen readers should use the following link to activate Accessibility Mode before continuing: Learn more and Activate accessibility mode.

Cryogenic Computing Complexity (C3) Program

Solicitation Number: IARPA-BAA-13-05
Agency: Office of the Director of National Intelligence
Office: Intelligence Advanced Research Projects Activity
Location: IARPA1
  • Print
:
IARPA-BAA-13-05
:
Modification/Amendment
:
Added: Jul 29, 2013 11:10 pm Modified: Aug 29, 2013 5:29 pmTrack Changes
Solicitation Number: Notice Type:
IARPA-BAA-13-05 Combined Synopsis/Solicitation

Amendment 01

This amendment corrects errors in the original BAA. Amended regions are highlighted in yellow.


1. Section 1.B. Program Metrics and Milestones. Table 10 Major Deliverables (page 23) is amended to correct an error on Cryogenic Memory Program Month for benchmark circuit chips deliverable item. The Program Month should read "15, 27, 39."
2. APPENDIX H: Government Furnished Foundry (GFF) Available to Performers. Table 14. GFF Process Development Roadmap (Preliminary) (page 63) is amended to correct an error in the unit of the Minimum JJ critical current under the column of Fabrication Process Attributes. The correct unit should be "μA."
Questions may be submitted to dni-iarpa-baa-13-05@iarpa.gov.



Original Synopsis:

Power and cooling demands of high performance computers are rapidly becoming unmanageable problems for the enterprises that depend on them. In 2012, the aggregate power demand of the TOP500 supercomputers was about 0.25 GW. The projected electrical power estimates for a 1 exaFLOP/s computer (where 1 exaFLOP/s=1018 floating point operations per second) are between 20 MW and several hundred MW. Today's high performance computers and the projected exascale computers employ the same complementary metal-oxide-semiconductor (CMOS) technologies that have supported decades of continuous increases in computer performance. This performance improvement has slowed down as the feature size approaches atomic dimensions. Furthermore, the problem with projected energy demands based on CMOS technology continues without any solution in sight.


Superconducting computing offers an attractive low-power alternative to CMOS with many potential advantages. Josephson junctions, the superconducting switching devices, switch quickly (~1 ps), dissipate little energy per switch (< 10-19 J), and communicate information via small current pulses that propagate over superconducting wires practically without loss. In the past, significant technical obstacles prevented serious exploration of superconducting computing, but recent innovations have created foundations for a major breakthrough. For example, the new single flux quantum (SFQ) logic circuits have no static power dissipation, and new energy-efficient cryogenic memory designs would allow operation of memory and logic in close proximity within the cold environment. Published studies indicate that superconducting computers may be capable of 1 PFLOP/s for about 25 kW and 100 PFLOP/s for about 200 kW, including the cryogenic refrigerator (1 PFLOP/s= 1015 floating point operations per second).


The goal of the C3 program is to demonstrate a small-scale computer based on superconducting logic and cryogenic memory that is energy-efficient, scalable, and able to solve interesting problems. The current BAA is for only phase 1 of the program, to develop the technologies required to demonstrate the value of superconducting computing. The program research consists of two technical thrusts:


• Cryogenic Memory (CM): Create new approaches to enable high performance computing systems with significantly improved memory capacity and energy efficiency compared to the state-of-the-art. Develop and demonstrate complete small-scale memories.


• Logic, Communications and Systems (LCS): Develop, fabricate, and test key superconducting logic circuits required to demonstrate the potential of superconducting logic for high performance computing. Develop a plan to integrate the components into a working computer.


Offerors may propose to one or both of these technical thrusts. A separate proposal is required for each thrust.


IARPA expects to issue a second BAA for phase 2 of the C3 program, which will be to scale and integrate the technologies developed in phase 1 into a working superconducting computer.


Contracting Office Address:
Office of the Director of National Intelligence
Intelligence Advanced Research Projects Activity
Washington, District of Columbia 20511
United States


Primary Point of Contact:
Dr. Marc Manheimer
Program Manager
dni-iarpa-baa-13-05@iarpa.gov

Please consult the list of document viewers if you cannot open a file.

Amendment 1

Type:
Mod/Amendment
Posted Date:
August 29, 2013
Description: Amendment 01 Description to IARPA-BAA-13-05

Amendment 2

Type:
Mod/Amendment
Posted Date:
August 29, 2013
Description: Amendment 01 to IARPA-BAA-13-05
:
Office of the Director of National Intelligence
Intelligence Advanced Research Projects Activity
Washington, District of Columbia 20511
United States
:
Marc Manheimer,
Program Manager